The level of integration and speed in semiconductor integrated circuits continue to increase. The next generation of dynamic memories will have a capacity of 256 Mb and that of microprocessors will have upwards of ten million transistors. Further generations are being planned. Clock rates are exceeding 300 MHz and are expected to exceed 1 GHz. The increased level of integration has been accomplished in part by shrinking the lateral sizes of the individual components.
However, the increasing proximity of features, in particular the long conductive interconnects extending horizontally on a complex integrated circuit, has introduced the problem of unintended interactions between those features. A complex integrated circuit must include a large number of horizontal interconnects linking active circuits in one part of the integrated circuit to those in another part. Simultaneous with the decrease in feature sizes, the overall size of the integrated circuit has continued to somewhat increase. As a result, the length of the interconnects, which are often laid in parallel for a sizable distance of their runs, has increased or at the best not decreased, and their separation in the horizontal plane has significantly decreased. The amount of electrical coupling, more precisely expressed in terms of parasitic capacitance, between such lines is generally proportional to the ratio of their length to their separation. That is, the coupling necessarily increases with decreasing line separation unless the overall size of the chip is reduced, and it is unlikely that chip size will be reduced in the long term.
Although the coupling problem seems to be worse within respective wiring levels, inter-level coupling can occur across the thin inter-level dielectric layers interposed between multiple horizontal wiring levels. In advanced integrated circuits, particularly those of microprocessors and other complex logic, there may be five or more wiring levels to provide the complicated interconnection paths. The thickness of these inter-level dielectric layers appears to be limited at somewhat less 1 .mu.m because of dielectric breakdown. However, even at these thicknesses, inter-level capacitance and resultant inter-signal coupling can become problems.
Another way of viewing this problem is to consider the RC charging time .tau. between a long interconnect and a large grounded neighboring and parallel feature. The charging time may be represented by EQU .tau.=R.multidot.C, (1)
where R is the resistance of the conductive interconnect and C is the capacitance between the interconnect and the grounded feature. The equation is somewhat more complicated for inter-line interaction, but the effect is much the same. For the extremely high speed operation required of advanced integrated circuits, the speed may be limited by the time constant associated with interconnects, which can be characterized by a maximum operation frequency f.sub.max, ##EQU1##
although there may be other factors near unity in this relationship. Generally in advanced circuits, the intra-level capacitance between parallel horizontal interconnects, such as in an internal bus extending over a substantial fraction of the chip, rather than the inter-level capacitance limits the operating speed of the chip.
Up till the present time, the increased speed has been accomplished in large part by decreasing the feature size and in particular decreasing the polygate length of the transistor, which increases its speed. However, as the feature sizes decrease below 0.18 .mu.m, the effects of the metallization begin to dominate. Therefore, the composition of the metallization and the dielectric constant of the insulator begin to dominate.
One of the motivators for changing from aluminum to copper for advanced integrated circuits as the material of the interconnect is to reduce the value of R because of the lower resistivity of copper compared to aluminum, the conventional material as of now. It is greatly desired that this substitution of copper for aluminum as the metallization material not be compromised by a concurrent increase in the value of the inter-line capacitance C across the dielectric material as the feature sizes of integrated circuits further decrease.
The electrical characteristics of a dielectric material are quantified by its resistivity and its dielectric constant. For an insulator in an integrated circuit, the resistivity must be fairly high, approximately 10.sup.14 ohm-cm or higher. The capacitance C of an planar capacitive structure, whether intentional or parasitic, can be represented as ##EQU2##
where A is the area of the capacitive plates, d is the gap between the plates, and k is the dielectric constant of the material filling the gap. The relationship is somewhat more complex for interconnects, but the important factors are the same. For an interconnect of constant width, its area A increases with its length L. Reduced dielectric constant k results in reduced capacitance, thus reducing the cross-talk and coupling, thus allowing increased operating speeds.
At the present time, the most common form of inter-level dielectric for integrated circuits is silicon dioxide or related silicate glasses, such as BPSG. These are all silicon-based materials having the approximate chemical composition SiO.sub.2. Hereafter, these will be collectively referred to as silica. The dielectric constant k for silica is between 3.9 and 4.2. That for Si.sub.3 N.sub.4, another common insulating material in present day integrated circuits, is even higher--7.5. For these reasons, there has been much recent interest in low-k dielectrics having a dielectric constant lower than 3.9.
Several low-k materials have been proposed for use as inter-level dielectric. For use in integrated circuit fabrication, any such material should at a minimum be compatible with other conventional chip processing steps. Some proposed low-k materials are silicon-based, for example, fluorinated silica glass (FSG, k=3.5), hydrophobic porous spin on glass (HPS, k=2.5.about.3), hydrogen-silsesquioxane (HSQ, k=2.5.about.2.9). Others are carbon-based, as will be discussed later. By a carbon-based material is meant a material containing on an atomic basis more carbon than either or both of silicon or oxygen. In contrast, a silicon-based material contains more silicon than carbon and is typically based on SiO.sub.2 or Si.sub.3 N.sub.4.
An example of an advanced structure to which it is desired to apply low-k dielectrics is a dual-damascene via, illustrated isometrically in FIG. 1. A via is an electrical contact through an inter-level dielectric layer separating two levels of metallization. A substrate 10 includes a copper horizontal interconnect 12 formed in its surface. Over the substrate are formed a lower stop layer 14, a lower dielectric layer 16, an upper stop layer 18, and an upper dielectric layer 20. The stop layers 14, 18 are dielectric layers having etching characteristics different than those of the dielectric layers 16, 20 such that a selective etch can be used which etches the dielectric layer but stops on the stop layer. One or more via holes 22 extend. through the lower dielectric layer 16 and the two stop layers 14, 18 down to corresponding copper interconnects 12, only one being shown in FIG. 1. The portion of the lower stop layer 14 at the bottom of the via hole 22 is removed in a post-etch soft plasma treatment following the main etching steps. A trench 24 extends through the upper dielectric layer 20 and connects at its bottom with the via holes 22.
There are two principal techniques for forming the dual-damascene structure, the self-aligned process and the counterbore dual-damascene process. In the self-aligned dual-damascene process, the lower stop layer 14, the lower dielectric layer 16, and the upper stop layer 18 are first deposited. Then, a photolithographic step forms an incomplete via hole principally in the upper stop layer 18. Thereafter, the upper dielectric layer 20 is deposited, and a photomask is formed over the area of the trench 24. A single etching step that selectively etches dielectric to material of both stop layers 18, 14 forms both the trench 24 in the upper dielectric layer 20 and the via 22 in the lower dielectric layer 16. On the other hand, in the counterbore dual-damascene process, both stop layers 14, 18 and both dielectric layers 16, 20 are deposited before a first photolithographic step etches an extended via hole from the top of the upper dielectric layer 20 to the lower stop layer 14. Then a second photolithographic step etches the trench 24 but stops on both stop layers 14, 18.
Once the structure of FIG. 1 has been formed, a metallization stack is deposited into the via holes 22 and the trench 24 in one deposition sequence, and the metal likely overflows over the top surface 26 of the upper dielectric. Chemical mechanical polishing (CMP) is then performed to remove all of the metallization above the upper dielectric surface 26. The metal filling the trench 24 provides for upper-level horizontal interconnects, and the metal filling the via holes 22 provides for inter-level vertical interconnects. The chemical mechanical polishing of a dual-damascene structure is particularly useful with copper metallization since it allows definition of copper vias and interconnects without a copper etching step. Copper is difficult to etch in a dry plasma, and presently available copper plasma etches are more expensive than the dual-damascene process.
The process of forming the dual-damascene structure of FIG. 1 is fairly well developed when the two dielectric layers are formed of silicon dioxide or related oxygen-based materials, which generally are called oxides. Silicon nitride forms effective stop layers for oxide dielectric layers since the chemistry is well known to selectively etch oxide over nitride. It is believed that presently available techniques for etching silicon-oxide can be modified for silicon-based low-k dielectrics.
However, one of the most promising of the low-k dielectrics is primarily carbon-based. This preferred material is formed from divinyl siloxane-benzocyclobutene (DVS-BCB), available under the trade name of Cyclotene.TM. 5021 from Dow Chemical Corporation of Midland, Mich. Its basic constituent includes monomers, as illustrated in FIG. 2, of two groups of benzocyclobutene 30 linked by the silicon-containing divinyl siloxane 32. This is dissolved in an organic solvent, such as mesitylene, in which it forms oligomers, such as the dimer illustrated in FIG. 3. After the solution is spun onto the wafer, it is dried and thermally cured to form a three-dimensional polymer illustrated in FIG. 4, consisting of groups 34 of tetrahydronapthalene. Each napthalene group 34 is linked on one end to another napthalene group 34 and on the other end to yet another napthalene group 34 and to one side of a siloxane group 36. The cured polymer of DVS-BCB is often simply referred to as BCB. Because of the multiple branching, it forms a 3-dimensional polymer. It has the advantage that, after the solvent has evaporated, no volatile byproducts evolve during curing. Further, no catalyst is required for polymerization. The polymer includes about 4% by weight of silicon, the remainder of the polymer being carbonaceous, mostly carbon and hydrogen with a little oxygen. It is believed that the small amount of silicon promotes the adhesion of the BCB to silica and other silicon-based materials commonly found in integrated circuits.
The use of BCB and other carbon-based dielectric materials introduces a question about the precision etching required of all inter-level dielectric layers in advanced integrated circuits. Advanced etching relies upon dry plasma etching. While techniques are well advanced for plasma etching silicon dioxide and silicon nitride, the etching of carbon-based materials, such as carbon polymers, is much less advanced. Nonetheless, low-k materials are being considered for very advanced structures, and it is greatly desired that etch processes be found which have capabilities similar to those for oxide and nitride etching. Cheung et al. in U.S. Pat. No. 5,679,608 disclose the use of BCB as a dielectric layer but do not provide any guidance on its etching.
Dow in their sales brochure "Cyclotene 5021: Integrated Circuit Dielectric Systems: Processing Procedures", 1996 recommends several combinations of etching gases for etching BCB, such as SF.sub.6 /O.sub.2, CHF.sub.3 /O.sub.2, and CF.sub.4 /O.sub.2, with or without an argon diluent and with moderate bias voltages of less than 200V. The fluorine component is recommended to etch the silicon fraction.
Lii et al. provide more process information for etching BCB with O.sub.2 /CF.sub.4 in "Low dielectric Dow Cyclotene 3022 (BCB) etch for multilevel interconnection integration," Proceedings of Fifth International Symposium on Ultra Large Scale Integration Science and Technology, Reno, Nev. May 23-26, 1995, Electrochemical Society Proceedings, vol. 95-5, 1995, pp. 266-274. Flanner et al. have also disclosed a method of etching BCB in "Etching characteristics of the low dielectric constant material Cyclotene*5021 (BCB) in the LAM TCP 9100 Etcher," 1998 Proceedings Fourth International Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC), Feb. 16-17, 1998, Santa Clara, Calif., DUMIC Catalog No. 98IMIC-333D, pp.61-64. Their etching method is directed to a dual damascene structure. It includes the chemical vapor deposition of a silica hard mask from silane. The hard mask is etched with C.sub.2 F.sub.6 /C.sub.4 F.sub.8 /Ar, and the BCB is etched with O.sub.2 /C.sub.2 F.sub.6 /Ar. They suggest that the addition of N.sub.2 lessens faceting of the hard mask but increases the bowing of the BCB.
It is greatly desired to use low-k dielectric materials in the dual-damascene structure of FIG. 1. Lii et al., ibid, disclose the formation of a damascene structure similar to that of FIG. 1 using BCB dielectric. However, they perform separate steps of depositing the BCB and etching it both for the via and for the trench. They also deposit the metal separately into the via and the trench with two CMP steps. That is, they use two single-damascene steps. It is desired to reduce the number of etching steps as well as CMP steps.
Yu in U.S. patent application, Ser. No. 09/069,568, filed Apr. 29, 1998, discloses a method of plasma etching BCB using an etching gas containing a combination of O.sub.2, N.sub.2, and Ar. The nitrogen is ascribed to improving anisotropic etching of the holes by forming a polymer on the sidewalls. She also has found that etch rates are increased by maintaining the wafer at a temperature of about 15 to 20.degree. C.
The use of photoresist by itself to mask the BCB etch is generally insufficient since photoresist is usually a carbon-based material, and it is expected that the etch selectivity between photoresist and the carbon-based low-k material will be poor. As a result, it is known to use hard mask of silicon oxide or silicon nitride, for example, as disclosed by Flanner et al., ibid. That is, a hard mask layer is deposited over the BCB and is photolithographically patterned.
The etching of the carbon-based material must satisfy the typical requirements for via etching, for example, etching of holes of high aspect ratio without etch stop and with vertical sidewalls.